Keynote Lectures

Edge of Chaos : The Elan Vital of Complex Phenomena

Prof. Leon Chua, University of Berkley, USA

Prof. Leon Chua received his M, 1961 and Ph.D., 1964 degrees from the MIT and the University of Illinois at Champaign-Urbana, respectively. He became an Assistant Professor of Electrical Engineering at Purdue University in 1964, and was promoted to Associate Professor in 1967. He joined the UC Berkeley in 1970. He is the first recipient of the 2005 Gustav Kirchhoff Award, the highest IEEE Technical Field Award for outstanding contributions to the fundamentals of any aspect of electronic circuits and systems that has a long term significance or impact. He was also awarded the prestigious IEEE Neural Networks Pioneer Award in 2000 for his contributions in neural networks.



Prof. Ronald Tetzlaff, Technical University of Dresden, Germany

Prof. Ronald Tetzlaff is a Full Professor of Fundamentals of Electrical Engineering at the Technische Universität Dresden, Germany. His scientific interests include problems in the theory of signals and systems, stochastic processes, physical fluctuation phenomena, system modelling, system identification, Volterra systems, Cellular Nonlinear Networks, and Memristive Systems. From 1999 to 2003 Ronald Tetzlaff was Associate Editor of the IEEE, Transactions on Circuits and Systems: part I. He was "Distinguished Lecturer" of the IEEE CAS Society (2001-2002). He is a member of the scientific committee of different international conferences. He was the chair of the 7th IEEE International Workshop on Cellular Neural Networks and their Applications (CNNA 2002), of the 18th IEEE Workshop on Nonlinear Dynamics of Electronic Systems (NDES 2010), of the 5th International Workshop on Seizure Prediction (IWSP 2011) and of the 21st European Conference on Circuit Theory and Design (ECCTD 2013). Ronald Tetzlaff is in the Editorial Board of the International Journal of Circuit Theory and Applications since 2007 and he is also in the Editorial Board of the AEÜ - International Journal of Electronics and Communications since 2008. He serves as a reviewer for several journals and for the European Commission. From 2005 to 2007 he was the chair of the IEEE Technical Committee Cellular Neural Networks & Array Computing. He is a member of the Informationstechnische Gesellschaft (ITG) and the German Society of Electrical Engineers and of the German URSI Committee.


From CMOS to Memristor Nanoelectronics: Search for Best Design Threading


Sung-Mo “Steve” Kang,
University of California, Santa Cruz, US
Jason K. Eshraghian,
University of Michigan, Ann Arbor, US


Since the 1970s, CMOS technology-based circuits and systems have revolutionized the microelectronics industry, in analog, digital and mixed signal fields. From the start, CMOS technology has overcome formidable competition from NMOS, bipolar, GaAs and other compound semiconductor technologies. The forceful advancement of CMOS technology has been empowered by advantages mainly in low power consumption and ease of design. However, single-digit feature sizes in CMOS nanotechnology downscaling face insurmountable roadblocks, such as fabrication limits, prohibitive costs, and limited dependability on the electrical charge quantity in high-density circuits. To highlight the challenges of commercialization, Global Foundries opted to bow out of the scaling race at the 7 nm node. Since HP’s announcement of nanoscale memristor fabrication in 2008, memristor technology has risen to be a strong companion technology to CMOS, by providing programmable resistance states in lieu of less-reliable charge storage.

The use of memristance (aka, memory resistance) can provide new means for reliable nanoscale memory design, instead of significantly less reliable charge variables in nanoscale DRAM or SRAM. For neuromorphic computing, crossbar arrays of memristors can compactly implement the weighted summation of input vectors, which is the core of CNN operations. It turns out that neuromorphic hardware can be implemented using memristors, which can parallelize a huge number of simple operations. This is precisely what is needed in the implementation of deep neural network accelerators with billions of parameters, making memristor-CMOS processing of neural networks superior over classical digital computers.

The first part of the talk will take a brief journey from the early stages of CMOS design to present memristor nanoelectronics with critical views and considerations for device threading, interconnect and circuit technologies for optimal system developments that achieve multidimensional design goals such as reliability, throughput performance, energy consumption, and manufacturing cost.

The second part of the talk will then apply these principles to neuromorphic systems, namely retina-inspired image processing and brain-driven computation. The powerful capabilities of these neuromorphic processors can be applied to a plethora of real-world challenges, from data-driven healthcare, to neurostimulation, and in AI-generated artwork, as we make a profound shift away from the sequential processing of Von Neumann machines towards parallel, interconnected neural-inspired structures.

Sung-Mo “Steve” Kang is a Distinguished Chair Professor and Dean Emeritus of the Jack Baskin School of Engineering, UC Santa Cruz, and Chancellor Emeritus of UC Merced and President Emeritus of KAIST. He was Department Head of Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign (UIUC). He has 16 U.S. patents granted, published over 500 papers, and co-authored 10 books. He has served as a member of the editorial boards and as a guest editor multiple times for both the Proceedings of the IEEE and the International Journal of Circuit Theory and Applications, the IEEE Transactions on Circuits and Systems, the Circuits, Signals and Systems, and as the Founding Editor-in-Chief of the IEEE Transactions on Very Large Scale Integration Systems. He was President of the IEEE Circuits and Systems (CAS) Society. He has received the IEEE CAS Society Meritorious Service Award, Technical Achievement Award, Education Award and the Society Award. He was a Visiting Professor at the University of Karlsruhe, the Technical University of Munich, the Technical University of Dresden, KAIST, and the Swiss Federal Institute of Technology, Lausanne. He is a Fellow of the IEEE, the Association for Computing Machinery (ACM), and the American Association for the Advancement of Science (AAAS). He received his Ph.D. degree from the University of California at Berkeley in electrical engineering. His research interest includes modeling and simulation of semiconductor devices; memristors and resistance-state memories, low-power VLSI design, nano-bioelectronic circuits, and neuromorphic computing.

Jason K. Eshraghian is a co-Track Chair for the Neural Systems and Applications Committee at the 2020 IEEE International Symposium on Circuits and Systems. He has received the 2019 IEEE Very Large Scale Integration Systems Best Paper Award, and a Best Paper Award at the 2019 IEEE Artificial Intelligence Circuits and Systems Conference. He is currently a Research Scientist with the Department of Electrical Engineering and Computer Science, University of Michigan at Ann Arbor, where his research is focused on neuromorphic computing using RRAM-CMOS integration. He received the Bachelor of Engineering (Electrical & Electronic) and the Bachelor of Laws degree, and Ph.D. from the University of Western Australia, Perth, WA, Australia. He has also been involved with the AI-healthcare industry as the CTO of iDataMap Corporation, and an Analog Design Engineer with HUMM Corp.